Many metal-oxide-semiconductor field-effect transistors (MOS FETs) for high voltage applications have a vertical structure. The term “vertical structure” or sometimes referred to as “a vertical MOS transistor” refers to the arrangement that the source terminal and the drain terminal of the vertical MOS transistor are positioned one over another. In contrast, “a planar MOS transistor” refers to the arrangement of a transistor that the source terminal and the drain terminal of the planar MOS transistor are positioned at substantially the same horizontal planar level. Compared with a planar MOS transistor occupying the same area in a semiconductor integrated circuit (IC) chip, a vertical MOS transistor is usable of withstanding a greater drain-to-source voltage difference and a greater current level and is configurable to have low turned-on drain-to-source resistance.